Senior Principal Hardware Emulation Engineer

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the team

The emulation team builds the pre-silicon model of SambaNova's RDU that the software, architecture, and verification teams depend on.

About the role

SambaNova is looking for a Senior Principal Engineer to build and own the hardware emulation models for our next-generation Reconfigurable Dataflow Unit — the silicon behind our AI workload acceleration systems.

Emulation is a development platform here, not a checkbox. Our software teams bring up drivers, runtime, and compiler against the emulation model months before silicon. Our architects measure performance on it. Our verification team runs on it to get through scenarios that simulation cannot reach in useful time. When the model is fast, accurate, and available, three organizations move faster; when it is not, they wait.

Building that model is the core of the job. You will work shoulder to shoulder with the RTL design team to keep the design emulation-compliant, decide where a vendor model will do and where you need to write a custom one, and own the automation that keeps the platform running tests continuously rather than by hand. This is a senior individual-contributor role, and much of its leverage comes through other teams: you will be the person design, verification, and software engineers consult on what emulation can and should do, and the one who holds our emulator vendors to account.

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_*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> Responsibilities

Build the models

Develop the emulation model for each new RDU generation: high-performance transactors, behavioral models, and memory models in SystemVerilog and C/C++

Partner with the RTL design team to keep the design emulation-compliant: review RTL and IP for constructs that will not map cleanly to the emulator, and close the gaps by substituting vendor emulation models or hand-coding custom models where no vendor model exists

Own model fidelity: make sure substituted and custom models track design intent closely enough that software, performance, and verification results can be trusted

Influence design decisions upstream so emulation-readiness is designed in rather than worked around

Own the platform, flows, and automation

Own the emulation environment architecture: build and runtime flows, partitioning, compile strategy, clocking, and memory configuration for each chip generation

Build and own the workflows that automate emulation testing on the hardware: job scheduling, regression launch, failure triage, and results reporting, so the platform runs continuously without manual babysitting

Own throughput and capacity: profile and remove bottlenecks in models, transactors, and testbench collateral so turnaround stays fast as the design grows

Own the emulator vendor relationship: drive blocking tool issues to resolution, hold the vendor accountable to our program s …